1. Field of Use
This invention relates to memory systems and more particularly to efficiently and reliably process a variety of memory requests in conjunction with performing internal operations involving access to memory.
2. Prior Art
It is well known to construct memory systems from a number of memory modules. In certain prior art systems, memory modules are paired together to provide a double word fetch access capability. The term double word fetch access as used herein refers to the capability of being able to access a pair of words at a time from a memory system during a cycle of operation. This type of system is described in U.S. Pat. No. 4,236,203, issued Nov. 25, 1980 entitled "System Providing Multiple Fetch Bus Cycle Operation", invented by John L. Curley, Robert B. Johnson, Richard A. Lemay and Chester M. Nibby, Jr., and assigned to the same assignee as named herein.
In the above prior art system, the memory system connects to an asynchronously operated single word wide bus. In the arrangement, a request for multiple words is made in a single bus cycle and the requested information words are delivered to the bus over a series of response cycles. While this arrangement improves the system throughput capabilities, it becomes desirable to be able to provide a memory system able to respond to a plurality of different types of requests involving the transfer of multiple words over a single bus accessed simultaneously during a series of cycles without incurring communication delays. This becomes desirable where it is desired to provide a high speed transfer of data to another memory device such as a cache unit or disk device.
The copending patent application "A Memory Controller with Interleaved Queuing Apparatus" Ser. No. 202,821, filed Oct. 31, 1980, of Robert B. Johnson and Chester M. Nibby, Jr. discloses apparatus which facilitates the processing of the above mentioned requests. In addition to processing a variety of different types of requests, the controller is required to respond to internal requests requiring access to memory. For example, such requests may involve the processing of refresh commands.
To minimize conflicts, one prior art controller performs refresh cycles of operation in parallel with certain types of memory operations. This controller is disclosed in U.S. Pat. No. 4,185,323 which is assigned to the same assignee as named herein. However, the types of memory operation is one which involves a single fetch access. Hence, in the case of double fetch operations, refresh commands necessitate interrupting the normal processing of memory requests. While this has produced minimum interference in processing memory requests specifying a sufficient number of single fetch accesses, there is increase in interference when the controller is required to process memory commands involving transfers of multiple groups of data words.
The copending patent application of Robert B. Johnson and Chester M. Nibby, Jr. entitled "A Memory Controller with Queue Control Apparatus" includes queue control circuits and cycle control circuits. The cycle control circuits operate to initiate memory cycles of operation when the queue control registers store memory requests which are being processed by the queue circuits and resolve conflicts between such requests and internally generated requests. Generally, the internal requests involve refresh operations performed in response to refresh command signals periodically generated for interrupting controller operations to perform a cycle of operation required for refreshing rows of memory elements within the controller's memory module units.
Such requests also include other types of requests requiring allocations of memory cycles, such as soft error rewrite cycle operations described in U.S. Pat. No. 4,359,771, issued Nov. 16, 1982, entitled "A Method and Apparatus for Testing and Verifying the Operation of Error Control Apparatus Included Within a Memory System" invented by Robert B. Johnson, et al.
While the above described cycle control apparatus resolved conflict situations, it was found that it could not ensure complete unambiguous resolution of such conflicts when modified to operate at increased performance levels. Also, in certain instances, the processing of queue requests were delayed so as to decrease memory efficiency.
Accordingly, it is a primary object of the present invention to provide improved memory cycle apparatus which permits a memory controller to efficiently process at high performance rates a variety of different types of memory requests which specify a multiword data transfer to a device.
It is a further object of the present invention to provide improved memory cycle apparatus for eliminating conflicts within a minimum of time between a variety of different types of memory requests and internal requests requiring consecutive memory cycles of operation thereby improving memory performance.